Walton Electronics Co., Ltd.

SGRAM-GDDR5 EMMC Memory Chips 32 Bit 4G 128MX32 SMD SMT

Product Details:
Place of Origin: original
Brand Name: original
Certification: ISO9001:2015standard
Model Number: EDW4032BABG-70-F-R
Payment & Shipping Terms:
Minimum Order Quantity: 10pcs
Price: 5.18-6.41 USD/PCS
Packaging Details: Standard
Delivery Time: 1-3 workdays
Payment Terms: T/T, Western Union,PayPal
Supply Ability: 10000pcs/months
  • Detail Information
  • Product Description

Detail Information

Packaging: Reel Mounting Style: SMD/SMT
Package / Case: FBGA-170 Supply Voltage: 1.3095 V-1.648 V
Memory Size: 4 Gbit FPQ: 2000
High Light:





EMMC Memory Chips 32 bit

Product Description

EDW4032BABG-70-F-R Original DRAM GDDR5 4G 128MX32 FBGA Memory



• VDD = VDDQ = 1.6V/1.55V/1.5V ±3% and 1.35V ±3%

• Data rate: 6.0 Gb/s, 7.0 Gb/s, 8.0 Gb/s

• 16 internal banks • Four bank groups for tCCDL = 3 tCK

• 8n-bit prefetch architecture: 256-bit per array read or write access for x32; 128-bit for x16 • Burst length (BL): 8 only

• Programmable CAS latency: 7–25

• Programmable WRITE latency: 4–7

• Programmable CRC READ latency: 2–3

• Programmable CRC WRITE latency: 8–14

• Programmable EDC hold pattern for CDR

• Precharge: Auto option for each burst access

• Auto refresh and self refresh modes

• Refresh cycles: 16,384 cycles/32ms

• Interface: Pseudo open drain (POD-15) compatible outputs: 40Ω pull-down, 60Ω pull-up

• On-die termination (ODT): 60Ω or 120Ω (NOM)

• ODT and output driver strength auto calibration with external resistor ZQ pin: 120Ω

• Programmable termination and driver strength offsets

• Selectable external or internal VREF for data inputs; programmable offsets for internal VREF

• Separate external VREF for address/command inputs

• TC = 0°C to +95°C

• x32/x16 mode configuration set at power-up with EDC pin

• Single-ended interface for data, address, and command

• Quarter data rate differential clock inputs CK_t, CK_c for address and commands

• Two half data rate differential clock inputs, WCK_t and WCK_c, each associated with two data bytes (DQ, DBI_n, EDC)

• DDR data (WCK) and addressing (CK)

• SDR command (CK)

• Write data mask function via address bus (single/ double byte mask)

• Data bus inversion (DBI) and address bus inversion (ABI)

• Input/output PLL on/off mode

• Duty cycle corrector (DCC) for data clock (WCK)

• Digital RAS lockout


32 bit
128 M x 32
4 Gbit
1.75 GHz
1.648 V
1.3095 V
0 C
+ 95 C
Cut Tape
Brand: Original in stock
Product Type: DRAM
Factory Pack Quantity: 2000
Subcategory: Memory & Data Storage


SGRAM-GDDR5 EMMC Memory Chips 32 Bit 4G 128MX32 SMD SMT 0


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