Product Details:
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Place of Origin: | original |
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Brand Name: | original |
Certification: | ISO9001:2015standard |
Model Number: | MPC852TVR50A |
Payment & Shipping Terms:
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Minimum Order Quantity: | 10pcs |
Price: | Contact us to win best offer |
Packaging Details: | Standard |
Delivery Time: | 1-3 workdays |
Payment Terms: | L/C, T/T, Western Union,PayPal |
Supply Ability: | 10000pcs/months |
Detail Information |
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Mounting Style: | SMD/SMT | Package / Case: | PBGA-256 |
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Number Of Cores: | 1 Core | Packaging: | Tray |
Processor Series: | PowerQUICC | ||
High Light: | MPC852TVR50A Microprocessors MPU,PBGA-256 Microprocessors MPU,UART Microprocessors MPU |
Product Description
MPC852TVR50A high quality Microprocessors MPU Ethernet 50 MHz Ethernet I2C SPI UART USB
Features
The following list summarizes the key MPC852T features:
• Embedded MPC8xx core up to 100 MHz
• Maximum frequency operation of the external bus is 66 MHz
— The 100MHz/80MHz core frequencies support 2:1 mode only
— The 50MHz/66MHz core frequencies support both 1:1 and 2:1 modes
• Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with 32, 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution
— 4-Kbyte data cache and 4-Kbyte instruction cache
– 4-Kbyte instruction cache is two-way, set-associative with 128 sets
– 4-Kbyte data cache is two-way, set-associative with 128 sets
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks
– Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and 16 protection groups
• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
• 32 address lines
• Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank
— Up to 30 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, flash EPROMs, and other memory devices
— DRAM controller programmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbyte–256 Mbyte)
— Selectable write protection
— On-chip bus arbitration logic
• Fast Ethernet controller (FEC)
• General-purpose timers
— Two 16-bit timers or one 32-bit timer
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
• System integration unit (SIU)
— Bus monitor
— Software watchdog
Product Category: | Microprocessors - MPU |
SMD/SMT | |
PBGA-256 | |
MPC852T | |
PowerPC | |
1 Core | |
32 bit | |
50 MHz | |
4 kB | |
4 kB | |
1.8 V | |
0 C | |
+ 95 C | |
Tray | |
Data RAM Size: | 8 kB |
I/O Voltage: | 3.3 V |
Interface Type: | Ethernet, I2C, SPI, UART, USB |
Memory Type: | L1 Cache |
Moisture Sensitive: | Yes |
Number of Timers/Counters: | 2 Timer |
Processor Series: | PowerQUICC |
Product Type: | Microprocessors - MPU |
300 | |
Subcategory: | Microprocessors - MPU |
Watchdog Timers: | Watchdog Timer |
Part # Aliases: | 935313682557 |
Unit Weight: | 0.058659 oz |
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